• Citizen

• Full Time

• Direct Hire

• UG :- - Not Required

• PG :- - Not Required

• No of position :- ( 1 )

• Post :- 10th Dec 2022

Minimum 3 years of experience in System Verilog HVL. Minimum 3 year of experience in OVM/UVM/VMM/Test Harness. Hands on experience of developing assertion, checkers, coverage and scenario creation. Must have executed at - least 2 SoC Verification projects Experience in developing test and coverage plan, Verification environment and validation plan. Knowledge of at - least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required. Review and Audit participation.

At - least 2 years of experience in handling team of 5 to 10 engineers. Define/derive Scope, Estimation, Schedule and Deliverables of proposed work. Assure compatibility of resources, tools, platform Work with customers through acceptance of deliverables. Effectively manage team members through coaching and mentoring and provide guidance and career planning to team - members.