Hi,
We are looking for Design verification engineer(SV UVM) for Thales India Engineering competency center(ECC Bangalore).
Qualifications: B. Tech in Electronics, Instrumentation engineering or equivalent with 3+ years of relevant experience. Higher qualifications of Post-graduation is desirable. Avionics and Defense systems design is desirable.
Responsibilities:
- Experience in Virtual Verification developing Test bench, Models, Checkers and Monitors using SV UVM.
- Development of Virtual Verification Procedures and Virtual Verification Report.
- Good hands on Python/Perl/TCL .
- Collaborative work applying quality standards and internal processes.
- Preparation of the associated project documentation and reviews.
Skills & experience:
- Must have strong experience in complete Hardware development life cycle (Technical feasibility, requirements, preliminary and detailed design, prototype manufacturing, test and evaluation, qualification and certification),
- Experience in Virtual Verification System Verilog UVM.
- Strong hands on Digital Design • Good hands on Python/Perl/TCL.
- Collaborative work applying quality standards and internal processes.
- Preparation of the associated project documentation and reviews.
- Must have experience to ensure the reporting progress of the project along with KPI.
- Must have experience to manage risks and opportunities.
- Must be rigorous, organized, autonomous and proactive, and motivated by a position within a multidisciplinary team.
- Must have demonstrated leadership skills on complex topics.