• Citizen

• Full Time

• Direct Hire

• UG :- - Not Required

• PG :- - Not Required

• No of position :- ( 1 )

• Post :- 10th Nov 2022

Sivaltech is hiring Design Verification, Physical Design, RTL Design, DFT, STA, and Embedded Software Engineers in India and the US. Sivaltech is a semiconductor services organization that provides Digital Design, Analog Design, Design Verification, Physical Design, DFT, and Embedded Software solutions to some of the worlds leading semiconductor companies. The environment is fast- paced and requires daily cross- functional interaction along with good communication, planning and execution skills.
Design verification engineers will likely have experience in functional or formal design verification. These candidates are expected to know the essential technical languages, disciplines, and methodologies that are generally tacked to this type of position.
Qualification Requirements :
At least 4 years of experience in ASIC verification including: Verification methodology using System Verilog, SVA, OVM/ UVM, Vera, or VMM
Experience in writing feature based test plans and implementing such test plans using one of the methodologies listed above
Experience running regressions, debugging test failures and achieving test plan targets
Knowledge in hardware description languages (HDL) such as Verilog, SystemVerilog and VHDL
Experience with Gate Level Simulation, Low Power Verification, Formal Verification are preferred Education Requirements:
Required :Bachelor's in Computer Engineering, Computer Science, Electrical Engineering, and / or related field
Preferred :Master's in Computer Engineering, Computer Science, Electrical Engineering, and / or related field
Hyderabad, India; Bangalore, India; Silicon Valley, CA; San Diego, CA; Dallas, TX and Austin, TX RTL/ Digital design engineers will design and implementation of SoC, Peripherals, Graphics, Modem, Bus and Network- on- chip cores. These candidates will understand and work on all aspects of the VLSI development cycle such as architecture, micro architecture, Synthesis/ PD interaction and design convergence and actively work with various core, verification, and physical design teams across multiple sites. They will perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification.

4- 10 years of solid experience in digital front- end design
Expertise in RTL coding in Verilog/ VHDL/ SV
Familiarity with various bus protocols like AHB, AXI is highly desired
Experience in low power design methodology and clock domain crossing designs
Experience in Spyglass Lint/ CDC checks and waiver creation
Experience in mobile Multimedia/ Camera design is a plus
Working knowledge of timing closure is a plus
Expertise in Perl, TCL language is a plus
Expertise in post- Si debug is a plus
Good documentation skillsability to create unit level test plans Physical design engineers are ideally creative, motivated, energetic, pleasant to work with, and put the needs of the team first. These candidates will be responsible for designs and test structures in RTL and GDSII as well as support areas regarding lint/ cdc/ P R/ Physical. These candidates may also participate in flow for advance process nodes ranging from 28nm and beyond. Supporting any EDA tool bench marking activities may be needed from time to time.
Qualification Requirements : 4+ years of industry experience in the following technical areas :

Physical design implementation (Floorplanning, CTS, and/ or STA) in advanced technologies
Power grid, clock tree, and low- power reduction implementation methods
Signal integrity and timing closure issues such as OCV/ AOCV/ Statistical Timing
Physical Verification, Conformal Low Power (CLP), IR drop analysis, and Formal Verification
Programming and scripting skills (Tcl, perl and/ or C)
Required :Bachelor's in Computer Engineering, Computer Science, Electrical Engineering, and/ or related field
Preferred :Master's in Computer Engineering, Computer Science, Electrical Engineering, and/ or related field
Hyderabad, India; Bangalore, India; Silicon Valley, CA; San Diego, CA; Dallas, TX and Austin, TX Job Function: DFT engineers will be responsible for DFT architecture and test methodology definition, and driving implementation primarily for Scan- based (ATPG) testing of high- end SoCs. These candidates likely lead a team DFT design and ATPG engineers and programmers to define DFT structures and tool flows needed for testing next- generation high- end server SoC products and drive their successful implementation. In addition to work within a DFT team, these candidates will work with hardware design teams to ensure successful implementation of various DFT structures in RTL, and they will work with SoC implementation teams on synthesis, physical design, clocking, timing, and design verification.
These candidates will also work with Product and Test Engineering (PTE) teams to drive successful bring- up of test vectors on ATE platforms. This role will span from current to future SoC products, and as such candidate activities will include strategy, design, methodology, and test execution. These candidates will interface with internal tool development teams and will be responsible for driving synergies that facilitate test insertion, clock design, and vector development automation. Finally, these candidates will work with tool vendors, such as Mentor Graphics and Synopsys, to define and integrate tool capabilities (particularly DFT insertion and ATPG) needed to implement and roll out DFT strategies.
Responsibilities include: Test strategy definition, DFT Architecture for large multi- core server chips, Logic specification and RTL design of DFT IP Software specification, DFT team leadership of related activities, ATPG test planning (including coverage, test time, test memory footprint on ATE Coordinates, cross- functional front- to- back SoC implementation and verification of DFT structures), and Bring- up of ATPG patterns on ATE.
Qualification Requirements : 3+ years of experience in the following technical areas :

Defining and executing DFT- related tool flows, spanning insertion, ATPG, as well as DFT requirements in front- to- back SoC implementation flows
Test vector planning for bring- up and production, and hand- on ATE bring- up experience
Achieving high coverage via SAF, TDF, as well as knowledge of other techniques such as Small Delay Defects, Path testing, LOC/ LOS, etc.
Tessent, DFTC, TCL/ PERL, IEEE 1149 and 1687, Primetime, SpyGlass, Verilog simulation including SDF, and Advantest ATE
Architecting automation strategies that align with third party DFT tools and creating further efficiencies
Leading large DFT/ ATPG teams
Defining/ bring- up of DFT architecture including hierarchical core/ chip based flows and pattern retargeting
Experience with large device test on ATE and with architecting DFT strategies in support of multi- core and parallel testing Education Requirements:
Required :Bachelor's in Computer Engineering, Computer Science, Electrical Engineering, and/ or related field
Preferred :Master's in Computer Engineering, Computer Science, Electrical Engineering, and/ or related field Location:
Hyderabad, India; Bangalore, India; Silicon Valley, CA; San Diego, CA; Dallas, TX and Austin, TX

SynthesisSTA engineers will perform RTL Synthesis to achieve the best Performance/ Power/ Area of the designs, DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation. These candidates will create Power Intent for the designs and verify power intent on RTL, run static Low- Power checks on gate level netlists, Verify Logic Equivalency Checks between RTL to Gates and Gates to Gates, setup signoff Static Timing Analysis and ECO flows and achieve timing closure working with the Design/ DFT/ PD teams, run Power Analysis and estimate power at RTL level, run Sign off Power Analysis on the P R data, support the DV team to enable gate level simulations with SDF and UPF aware simulations, and support functional eco rollout with automated ECO flows.

Experience with Synopsys tools for ASIC Synthesis and Timing Constraints and DFT implementation that includes MBIST and Scan
Experience with sign- off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks
RTL design experience with Perl/ TCL/ Makefile scripting
Experience with Power Analysis using Power Artist and PTPX
Experience with full- chip static timing analysis through tapeout, gate level simulations, and Functional ECO implementation with Automated flows Post- Silicon validation engineers will be self- motivated and will perform post- Silicon device level and system level validation and debugging. These candidates will need to have strong SW development background and should have worked in firmware development for complex SoCs- . Working experience with ARM debugger, CoreSight, JTAG, Lauterbach Trace 32 are required. The ideal candidate should leverage their knowledge and experience to provide leadership, technical guidance, and proper execution of silicon validation

4+ years of experience in embedded software/ silicon validation
Experience with writing and reviewing validation test plans
Experience with creating validation suite and building automation
Experience with development of directed, random, and pseudo- random diagnostics for validation in compliance with Silicon specifications
Debug of diagnostics on various platforms using JTAG, Logic Analyzers, Oscilloscopes and similar equipment will be required
Interaction with various engineering teams (e.g. systems, hardware design, design validation, software engineers, test engineering) in test- environment bring- updevelopment in order to meet team goals and resolve problems in a timely, effective and professional manner will be required
ARM System- On- Chip Pre- Silicon emulation and Post- Silicon ASIC Validation experience related to board bring up and debug
Have hands on experience of SOC architecture, micro- processor verification, and silicon debug environments
Hands on experience of processor programming and simulation IoT/ Wearables embedded systems engineers will be a part of a team of developers with expertise in low- level device driver software and HW/ SW interfaces. The candidates are proficient in C, and JTAG based hardware debugger (preferably Lauterbach usage) knowledge is required. These candidates will need a very good understanding of ARMv7/ ARMv8/ x86 architectures and will need to know how to utilize off- target development and debugging platforms in- addition to on target development. Strong familiarity and understanding of Operating System internals, RTOS Internals and Linux Internals is very useful. These candidates will work with minimal supervision, perform task definition, and work breakdown including time estimation as well as create, document and execute detailed test plans. These candidates will work closely with hardware design engineers to successfully drive projects to completion.

2 - 6 years of development and test experience in embedded software and firmware
Good working experience in using IAR/ Keil development environment
Required :Bachelor's in Computer Engineering, Computer Science and / or Electrical Engineering
Preferred :Master's in Computer Engineering, Computer Science and / or Electrical Engineering Storage embedded systems engineers will be talented, motivated and experienced. These candidates will have expertise in SAS/ SATA/ NVMe/ UFS and will need a very good understanding of SAS/ SATA/ NVMe/ UFS protocol. These individuals need to know how to utilize off- target development and debugging platforms in- addition to on target development. Strong familiarity and understanding of Operating System internals, Linux Internals, and RTOS will be very useful. These candidates will work with minimal supervision, perform task definition, and work breakdown including time estimation as well as create, document and execute detailed test plans. These candidates will work closely with hardware design engineers to successfully drive projects to completion.

2 6 years of development and test experience in storage firmware
Experience with SAS/ SATA/ NVMe front end and back end firmware
Experience in FTL, Wear- levelling and garbage collection algorithms
Good working experience in using ARM developer studio Mobile/ Consumer electronics embedded systems engineers will be talented, motivated, experienced, and have expertise in Linux. This role includes software design and development, and debugging of Linux and Linux/ Android software. The primary focus is the Linux/ Android platform level software (excluding the Linux kernel). These candidates will work with various internal cross- functional teams as well as third party OEMs in designing, developing and guiding new features that are scalable, performance and power optimized. Prior experience with WIFI, Peripherals, and/ or Multimedia protocol is plus.