Required Skills

static timing analysis Perl System verilog Silicon

Work Authorization

  • Citizen

Preferred Employment

  • Full Time

Employment Type

  • Direct Hire

education qualification

  • UG :- - Not Required

  • PG :- - Not Required

Other Information

  • No of position :- ( 1 )

  • Post :- 10th Nov 2022



Synthesis & STA engineers will perform RTL Synthesis to achieve the best Performance/Power/Area of the designs, DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation. These candidates will create Power Intent for the designs and verify power intent on RTL, run static Low- Power checks on gate level netlists, Verify Logic Equivalency Checks between RTL to Gates and Gates to Gates, setup signoff Static Timing Analysis and ECO flows and achieve timing closure working with the Design/DFT/PD teams, run Power Analysis and estimate power at RTL level, run Sign off Power Analysis on the P&R data, support the DV team to enable gate level simulations with SDF and UPF aware simulations, and support functional eco rollout with automated ECO flows.

Qualification Requirements :

  • Experience with Synopsys tools for ASIC Synthesis and Timing Constraints and DFT implementation that includes MBIST and Scan
  • Experience with sign- off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks
  • Experience with Verilog and System Verilog
  • RTL design experience with Perl/TCL/Makefile scripting
  • Experience with Power Analysis using Power Artist and PTPX
  • Experience with full- chip static timing analysis through tapeout, gate level simulations, and Functional ECO implementation with Automated flows
  • Education Requirements:
  • Hyderabad, India; Bangalore, India; Silicon Valley, CA; San Diego, CA; Dallas, TX and Austin, TX

Company Information