Verification Engineer / India / Bengaluru / 8 Years Experience

Required Skills

ASIC Verilog assembly language block level UVM verification environment top level transactor memory cache operation constrained randomization C language System Verilog UVM methodology

Work Authorization

Citizen

Preferred Employment

Full Time

Employment Type

Direct Hire

education qualification

UG :- - Not Required
PG :- - Not Required

Other Information

No of position :- ( 1 )
Post :- 18th Jun 2022

JOB DETAIL

SOC level firmware, System Verilog and UVM
Debug tests, design verification, system validation, vector generation, write all types of coverage measures for stimulus and corner-cases
Deliver detailed test plans

Required Candidate profile

System Verilog and UVM, assembly language, C language, Verilog, System Verilog, constrained randomization, block level, top level transactor, memory cache operation, UVM verification environment

Verification Engineer