• Citizen

• Full Time

• Direct Hire

• UG :- - Not Required

• PG :- - Not Required

• No of position :- ( 1 )

• Post :- 10th Nov 2022

RTL / Digital Design Engineers (RTL) Lead ASIC Verification Engineers [Ref:102] RTL / Digital Design Engineers (RTL) Job Function: RTL / Digital design engineers will design and implementation of SoC , Peripherals , Graphics , Modem , Bus and Network - on - chip cores. These candidates will understand and work on all aspects of the VLSI development cycle such as architecture , micro architecture , Synthesis / PD interaction and design convergence and actively work with various core , verification , and physical design teams across multiple sites. They will perform RTL design , simulation , synthesis , timing analysis , lint check , clock domain crossing check , conformal low power check , and formal verification. Qualification Requirements : 4 - 10 years of solid experience in digital front - end design Expertise in RTL coding in Verilog / VHDL / SV Familiarity with various bus protocols like AHB , AXI is highly desired Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint / CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow Experience in mobile Multimedia / Camera design is a plus DSP / ISP knowledge is a plus Working knowledge of timing closure is a plus Expertise in Perl , TCL language is a plus Expertise in post - Si debug is a plus Good documentation skills ability to create unit level test plans Education Requirements: Required : Bachelor's in Computer Engineering , Computer Science , Electrical Engineering , and / or related field Preferred : Master's in Computer Engineering , Computer Science , Electrical Engineering , and / or related field Location: Hyderabad , India; Bangalore , India; Silicon Valley , CA; San Diego , CA; Dallas , TX and Austin , TX