Required Skills

Graphics Automation ASIC VLSI FPGA SOC VMM Perl PCIE Gaming

Work Authorization

  • Citizen

Preferred Employment

  • Full Time

Employment Type

  • Direct Hire

education qualification

  • UG :- - Not Required

  • PG :- - Not Required

Other Information

  • No of position :- ( 1 )

  • Post :- 19th Jul 2022


  • The verification team is looking for a Senior Design Verification Engineer 2 to contribute on the verification of Network on Chip IPsand Subsystems.
  • The individual will help architect, develop and use simulation and/or formal based verification environments,
  • at block and subystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystem and SOC designs.


  • Plan verification of complex digital design blocks by fully understanding the architecture and design specification
  • Interact with architects and design engineers to create a comprehensive verification testplan
  • Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
  • Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
  • Debug tests with design engineers to deliver functionally correct design blocks
  • Identify and write coverage measures for stimulus quality improvements
  • Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

General requirements

  • Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs
  • Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification
  • Strong understanding of different phases of ASIC and/or full custom chip development is required
  • Experience in block level NOC (Network on Chip) verification is a plus
  • Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus
  • Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus
  • Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus
  • Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus
  • Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus

Special Requirements

Must have at least 1 year of prior work experience in each of the following

  • Architect and implement verification environment using advanced verification methodology such as UVM or SystemVerilog;
  • Test plan development and test writing;
  • Analyzing and debugging failures using simulation tools such as Synopsys VCS or DVE to verify hard IPs, FPGA fabric or System-on-Chip;
  • Functional coverage writing, coverage collection and analysis, coverage closure;
  • Writing System Verilog assertions and assertion based verification; and,
  • Running regressions, automation using scripting languages such as PERL and verification closure

Education Requirements

  • Masters / B.Tech / M.Tech
  • Experience : 5+ / 8-12 years of relevant experience.

Company Information