Required Skills

Debugging Computer architecture Mixed signal design PCIE Silicon

Work Authorization

  • Citizen

Preferred Employment

  • Full Time

Employment Type

  • Direct Hire

education qualification

  • UG :- - Not Required

  • PG :- - Not Required

Other Information

  • No of position :- ( 1 )

  • Post :- 11th Nov 2022


A key component of our system is the high-speed interconnect. The SERDES Senior/Staff Designer would be in charge of a core part of the high-speed PHY, including PCIe, Ethernet, and USB, in advanced FinFet technology nodes. A strong understanding of analog/mixed-signal circuit theories, and expert hands-on design skills, are keys to a successful candidate for this position.

Key Requirements

  • Strong understanding of analog/mixed-signal design theories and practical concepts such as mismatch, ratio-metric, linearity, stability, noise, and low-power
  • Strong understanding of one of the following core components of a high-speed PHY: CDR, PLL, PI, CTLE, TX Driver, Serializer/De-Serializer
  • Experience in circuit tradeoff analysis and ability to comprehend system-level specs and their impacts on circuit design, knowledge of PAM4 systems is a plus.
  • Understanding of the physical layout requirements and hands-on ability to perform critical layouts, experience in FinFet a plus
  • Proven track record of successful tape out and silicon meeting performance and power specifications, and experience in chip debug / validation / characterization.
  • The ability to communicate technical issues and present technical reviews coherently and logically are essential.

Company Information