• Citizen

• Full Time

• Direct Hire

• UG :- - Not Required

• PG :- - Not Required

• No of position :- ( 1 )

• Post :- 19th Jul 2022

Mandatory:

• Good understanding of FPGA architecture & hands-on experience building FPGA designs

• At least 2-3 years of experience using Xilinx Vivado & tool flows

• Strong in Verilog/SystemVerilog HDL & Digital Design

Good to have:

• Hands-on Experience working with Processor based Systems/SoCs

• Exposure to FPGA prototyping/emulation flows using Cadence or Synopsys tools

• Experience in Video pipelines using MIPI CSI/DSI; HDMI, Display Port Protocols

• Protocol knowledge on AXI/APB/I2C

• Basic scripting knowledge Python/Tcl/shell