Required Skills

Fabrication ASIC Digital design USB Ethernet Packaging Perl System verilog UVM Python

Work Authorization

  • Citizen

Preferred Employment

  • Full Time

Employment Type

  • Direct Hire

education qualification

  • UG :- - Not Required

  • PG :- - Not Required

Other Information

  • No of position :- ( 1 )

  • Post :- 16th Jul 2022


We have the following requirements to be complied:

  1. The applicant must be a bachelor of Engineering or technology (B.E. / B.Tech) BE or Master of Engineering or Technology (M.E / M.Tech)
  2. The candidate must demonstrate strong Digital Design Fundamentals, Knowledge on Analog Design is an added advantage.
  3. The candidate must have a strong syntactic and semantic understanding of System Verilog HDL.
  4. The candidate must have a relevant experience in any one (or more) of the verification methodologies viz. UVM / VMM / OVM. And should have a ready-reckoning knowledge on implementation specifics of the methodology.
  5. The candidate should have proficient expertise on test plan creation and execution, and must demonstrate metric-driven verification closure.
  6. Knowledge of productive languages is expected, it will be an added advantage if the candidate has know-how on any one of scripting languages like Perl / Shel / Python / TCL / Jenkins.
  7. Basic knowledge on mainstream protocols like PCIe/SATA/USB/Ethernet is expected, Advanced knowledge is an added advantage.

Company Information