We have the following requirements to be complied:
The applicant must be a bachelor of Engineering or technology (B.E. / B.Tech) BE or Master of Engineering or Technology (M.E / M.Tech)
The candidate must demonstrate strong Digital Design Fundamentals, Knowledge on Analog Design is an added advantage.
The candidate must have a strong syntactic and semantic understanding of System Verilog HDL.
The candidate must have a relevant experience in any one (or more) of the verification methodologies viz. UVM / VMM / OVM. And should have a ready-reckoning knowledge on implementation specifics of the methodology.
The candidate should have proficient expertise on test plan creation and execution, and must demonstrate metric-driven verification closure.
Knowledge of productive languages is expected, it will be an added advantage if the candidate has know-how on any one of scripting languages like Perl / Shel / Python / TCL / Jenkins.
Basic knowledge on mainstream protocols like PCIe/SATA/USB/Ethernet is expected, Advanced knowledge is an added advantage.