Uttar Pradesh - Noida

1 Year

- /- ( )

Required Skills

Health insurance VHDL Linux FPGA Hardware design Verilog Perl Design Engineer Trainee bash scripting Python

Work Authorization

  • Citizen

Preferred Employment

  • Full Time

Employment Type

  • Direct Hire

education qualification

  • UG :- - Not Required

  • PG :- - Not Required

Other Information

  • No of position :- ( 1 )

  • Post :- 4th Jun 2022

JOB DETAIL

  • Candidates should be B.Tech.CS MCA freshers/graduate
  • Basic Knowledge in Verilog, VHDL, SystemVerilog C
  • FPGA, EDA Tools, Linux, Perl, Python, Tcl, Bash scripting
  • Should have excellent communication skills
  • Ability to work independently with little supervision as well as ability to work within a team
  • Excellent multi-tasking skills
  • Self-motivated with strong team spirit

Company Information

Agnisys Technology pvt .ltd

support@agnisys.com

09783496949